When a plurality of monitor cameras are used by switching, the use of a zero crossing point of a commercial power supply is a known method of synchronizing video signals of the cameras. In this case, since the clocks in the system are synchronized based on the zero crossing point of the commercial power supply, when the frequency of the commercial power supply changes, the clocks in the system also change. Therefore, when color modulation is performed based on the changed clocks in the system, the frequency of a subcarrier also changes.
According to the C.C.I.R Report (C.C.I.R [1970-1974] Report XIII/624, CHARACTERISTICS OF TELEVISION SYSTEMS), the frequency of subcarrier for performing color modulation by, for example, the NTSC system is 3579535 Hz to 3579555 Hz. Since very high precision is required, in practice, it is difficult to perform a color modulation by using the clocks in the system as they are.
In order to solve the above-mentioned problems, it is necessary to convert a transfer clock for digital data (i.e., convert the clock from CLKA into CLKB) using, for example, a circuit shown in FIG. 3. In FIG. 3, DFFA represents a D-type flip-flop that receives input digital data DATA in synchronization with a rise of a clock CLKA, and outputs the digital data. DFFB is a D-type flip-flop that receives the output digital data D&lt;1:0&gt; from the D-type flip-flop DFFA in synchronization with a clock CLKB that is different from the clock CLKA, and outputs digital data OUT. Each of the D-type flip-flops DFFA and DFFB is arranged by a circuit like the one shown in, for example, FIG. 10.
Note that, in the circuit shown in FIG. 3, it is necessary to satisfy conditions: (a) the clock CLKA and clock CLKB are synchronized with each other, and a predetermined delay is introduced between the output of the D-type flip-flop DFFA in the front stage and the input of the D-type flip-flop DFFB in the back stage; or (b), when such a delay is not introduced, the clock CLKA and clock CLKB are synchronized with each other, and a predetermined phase difference is present between these clocks.
In (b), for example, if these clocks are not synchronized with each other, there is a possibility that the clocks CLKA and CLKB rise at substantially the same time. For instance, as shown in the timing chart of FIG. 4, when the clocks CLKA and CLKB rise at substantially the same time, and when the hold time and the setup time required by the D-type flip flop (latching element) are not ensured sufficiently, it is not certain what data is outputted as an output OUT from the D-type flip-flop DFFB shown in FIG. 3 in a period indicated by hatching in FIG. 4.
The hold time is a period after the edge of the clock, in which data needs to be retained by the latching element. The setup time means a period before the edge of the clock, in which the data needs to be kept by the latching element.
In a prior art (first prior art), in order to solve a problem associated with the substantially simultaneous rise of the clocks CLKA and CLKB, a PLL (phase locked loop) circuit shown in FIG. 7 is used for the control of the phases of the former and latter clocks. As shown in FIG. 7, the PLL circuit includes clock generators 21 and 22, frequency dividers 23 and 24, and a phase comparator 25. The clock generators 21 and 22 generate the clocks CLKA and CLKB, respectively. The frequency dividers 23 and 24 divides the clocks CLKA and CLKB into clocks CLKA2 and CLKB2 (CLKA2=CLKB2), respectively. The phase comparator 24 compares the phases of the clock CLKA2 (reference clock) and the clock CLKB2, and feeds an error output, that varies according to the phase difference, back to the clock generator 22. Such a circuit structure allows the clocks CLKA and CLKB to be synchronized with each other. In the case of (b), the control is carried out so that these clocks are synchronized with each other and a predetermined phase difference is present between the clocks.
In addition, as other prior art (second prior art), Japanese Laid-open Patent Application "Tokukaihei No. 1-261908" is known. This publication discloses a circuit that (1) divides by 1/N a clock of the latching element in the back stage, samples the resultant clock in accordance with a clock of the latching element in the front stage, (2) produces N-phase clocks whose phases differ from each other in accordance with the clock of the latching element in the back stage which has been divided by 1/N and sampled by the clock of the latching element in the front stage, (3) generates N rows of data whose data change points differ from each other by sampling rows of data in accordance with the N-phase clocks, and (4) selects and outputs N rows of data using a time window produced based on the clock of the latching element in the back stage.
According to the second prior art, when converting a row of data having the frequency of the clock of the latching element in the front stage into the frequency of the clock of the latching element in the back stage, the frequency is divided by 1/N so that the converted clock satisfies the sampling theorem. The clock whose frequency has been divided by 1/N is sampled in accordance with the clock before converted. The conversion of clock is carried out using the clock of the latching element in the back stage which was divided by 1/N. As described above, since the conversion of the clock is performed using the clock which was sampled by the clock before converted, the change point of data is not sampled. Thus, N rows of data with different change points are generated according to the clock of the latching element in the back stage, which was divided by 1/N. These rows of data are selected by a time window produced based on the clock of the latching element in the back stage. By selecting these rows of data using the time window, the change point of data is not sampled in performing the final conversion of clock.
However, the above-mentioned prior arts suffer from the following drawbacks. First, in the structure of the first prior art, the phases of both of the clocks are synchronized with each other using a PLL circuit. However, even when the PLL circuit is used, in FIG. 7, since the frequency of the clock CLKB is changed, the precision is improved as compared to the structure using the clock of the system. However, it is still impossible to avoid the change of frequency. Moreover, since both of a digital circuit and an analog circuit are used, the cost, chip area, and the restrictions relating to design increase.
Furthermore, in the second prior art disclosed in the above-mentioned publication "Tokukaihei No. 1-261908", when the frequency f.sub.1 of the clock CK1 and the frequency f.sub.2 of the clock CK2 shown as examples in FIG. 11 satisfy the relationship, for example, f.sub.2 =2.times.f.sub.1, the cycle of the clock (1/2) CK2 and the cycle of the clock CK1 are identical. In this case, whenever the clock CK1 rises in the D-type flip flop 5 shown in FIG. 11a a latching mistake may occur depending on the timing of the rise of the clock CK1 and the clock (1/2)CK2, causing an incorrect operation. Additionally, when N in f.sub.2 =N.times.f.sub.1 is a positive even integral or a number near the integral number, since the state continues in which the clock CK1 and the clock (1/2)CK2 rise at substantially the same time, a latching mistake may occur like the above.